[sv-bc] data for keywords proposal

While there may be disagreement on the technical aspects of Stu's proposal,
there is definitely a backward-compatibility problem caused by the large
number of keywords added in SystemVerilog and the particular keywords used.
Attached is some data based on a suite of actual customer designs. Over
half of them will not compile in SystemVerilog due to keyword issues.

Steven Sharp
sharp@cadence.com

List of SystemVerilog keywords used as identifiers in a suite of
67 customer Verilog designs. The list gives the number of designs
using a particular keyword. 57% of the designs use at least one
SystemVerilog keyword, and will not compile under SystemVerilog.

17 "bit"
12 "do"
11 "type"
8 "ref"
6 "priority"
5 "int"
5 "string"
4 "final"
3 "byte"
3 "expect"
3 "rand"
2 "assert"
2 "context"
2 "continue"
2 "logic"
2 "null"
2 "sequence"
1 "break"
1 "class"
1 "dist"
1 "interface"
1 "matches"
1 "new"
1 "protected"
1 "return"
1 "static"
1 "virtual"
1 "wait_order"
Received on Tue Dec 14 14:29:14 2004