[sv-bc] Re: [P1800] Re: DataTypes - Please vote no

Hi, Kev -

You have good points and I hope you have looked at the Data Types proposal
from an AMS viewpoint so that you can keep us honest.

What concerns me from your email is that I am obviously still not getting
my point across. I do not want any semantic changes. I want a relatively
simple syntax change.

Whatever a Verilog-2001 engineer previously declared to be a reg, I would
like to now have the option to declare the same variables as wires. Wires
assigned in an always block should have the exact same behavior as regs in
Verilog-2001. Any attempt to make continuous assignments (or any other
driver assignment) to a wire that is also assigned within a procedural
block shall be an error (just the same as if you had tried to declare reg
y; and wire y; with corresponding assignments in Verilog-2001).

The only complexity that I see from this proposal is that vendors will not
know if a wire declaration uses variable-assignment semantics or
net-assignment semantics until first usage is found in the module. I
believe this is minor, but it solves one of the most nagging complaints
that exists in Verilog today, and it also facilitates coding (it is also
real easy to teach!)

Example:

module myand3 (output y, input a, b, c);
   assign y = a & b & c;
endmodule

for whatever reason, I decide I want the functionality to be placed in an
always block:

module myand3 (output reg y, input a, b, c); // had to add reg to the
ANSI-style port - WHY??
   always @*
     y = a & b & c;
endmodule

with the enhancment:

module myand3 (output y, input a, b, c); // no need to declare reg y
   always @*
     y = a & b & c;
endmodule

This is a very simple example. From here, the

At 10:31 AM 12/14/2004, Kevin Cameron wrote:

>IMO it would be a bad idea to change how this stuff works without
>considering the impact on mixed signal extensions. If you want to propose
>different syntax/semantics for reg/wire, try including the use of drivers
>(and receivers) of different types (other than logic) in the same module
>and how resolution will work.
>
> From the perspective of low-level gate and transistor modeling VHDL is
> badly broken, I wouldn't like to see the same semantics turn up in Verilog.
>
>Kev.

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Received on Tue Dec 14 17:54:54 2004