I don't like goals (4) & (5).
I think the "first usage" approach is a bad idea and unnecessary.
For AMS purposes a reg declaration is viewed as the declaration of a
driver (that is shared between the processes in a module). If you are
going to drop the reg I would prefer that each process has its own
(implicit) driver, procedural blocks then behave the same as continuous
assignments. That behavior also matches VHDL's creation of drivers,
which will make translation easier - as well as manual inlining of
sub-modules.
The addition of uwire would appear to me to make (5) mostly redundant,
and it's a check you could do with a command-line switch - I don't see
the need to add the single-behavioral driver restriction.
I also don't see why you need a "universal" type, all you need is a
module default for the drivers - which could be "logic" in the absence
of anything else. I'd like to propose that you be able to type the
driver in the process instead of doing it at the module level e.g.:
module foo (inout wire Q, input clk, input bool data, input
blow_fuse)
initial begin
bool Q; // this process treats Q as bool
forever begin
@clk;
Q = data;
end
end
initial begin
logic Q; // this process treats Q as logic
Q = 1'bZ; // disabled
forever begin
@blow_fuse;
if (1'b1 == blow_fuse) Q = 1'bX;
end
end
...
- but that's not particularly interesting unless you can drive more
types onto a wire and have a way of resolving them, which is what AMS
does, so I'd rather leave this stuff until we are considering
multi-type resolution
and/or AMS issues.
Kev.
-----Original Message-----
Hi, All -
For the past six years, I have been trying to fix the annoying
requirement
that forces engineers to declare procedural variables or change
declarations when procedural variables are moved to continuous
assignments
or vice versa.
Attached is another attempt to fix this problem and satisfy past
concerns.
Please give it a peak and respond.
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Thu Dec 16 17:29:45 2004
This archive was generated by hypermail 2.1.8 : Thu Dec 16 2004 - 17:29:49 PST