Re: [sv-bc] unpacked wire array assignment

I've opened erratum 357 to track this issue, and marked it 'immediate'.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Rich,
Dave
Sent: Friday, January 28, 2005 11:39 AM
To: Surrendra Dudani; sv-bc@eda.org
Subject: RE: [sv-bc] unpacked wire array assignment

Surrendra,

Your assumption is correct. The rule was specifically put there because
there was no type equivalence for wires at the time. I remember bringing
this up at one of the data type on wires sub group meetings and we
agreed this rule should be removed, but I guess it slipped through the
cracks.

Dave

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Surrendra Dudani
> Sent: Friday, January 28, 2005 11:22 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] unpacked wire array assignment
>
> Another issue I found while reading Section 4.7 on array assignments.
> For unpacked array assignments, rules for wires require element
assignment
> compatibility, while rules for variables require element equivalence.
This
> may have been ok before as wires were not types and no equivalence
could
> be
> established, but with the introduction of types on nets, it seems
> unreasonable to have different rules. Does anyone know the reason for
this
> difference ?
> Surrendra
>
>
>
>
> **********************************************
> Surrendra A. Dudani
> Synopsys, Inc.
> 377 Simarano Drive, Suite 300
> Marlboro, MA 01752
>
> Tel: 508-263-8072
> Fax: 508-263-8123
> email: Surrendra.Dudani@synopsys.com
> **********************************************
Received on Fri Jan 28 12:27:38 2005