[sv-bc] FW: P1800 WG ready for ballot - SystemVerilog and Verilog 1364

 


________________________________

	From: Johny Srouji [mailto:srouji@us.ibm.com] 
	Sent: Tuesday, February 22, 2005 5:16 PM
	To: ieee1800@eda.org; Chuck AdamsJr; vberman@cadence.com;
peter@ashenden.com.au
	Cc: Arif.Samad@synopsys.com; Brad.Pierce@synopsys.com;
chas@cadence.com; fhaque@cisco.com; Ghassan.Khoory@synopsys.com;
Karen.Pieper@synopsys.com; Maidment, Matthew R;
Mehdi.Mohtashemi@synopsys.com; Neil.Korpusik@Sun.COM;
tom_fitzpatrick@mentorg.com; btf@boyd.com; etf@boyd.com; ptf@boyd.com;
sv-bc@eda.org; sv-ac@eda.org; sv-cc@eda.org; sv-ec@eda.org
	Subject: P1800 WG ready for ballot - SystemVerilog and Verilog
1364
	
	

	Hi All,
	
	After an outstanding effort by all of you, we are now at the
stage of SystemVerilog Draft 4.0 ballot and Verilog 1364 Draft 6.0
ballot. The
	ballots open today, 22 February 2005 and will close on 24 March
2005. Interested entities have registered for these ballots and their
primary Designated Representatives (DRs) should have received a
confirmation via receipt of their SA entity number, which is needed to
officially ballot at the IEEE ballot web site.
	
	The IEEE will be sending an email with the URL for access to the
official ballot drafts. If you have registered for this ballot, and you
do not
	receive this email, please let me or Andrew Ickowicz,
a.ickowicz@ieee.org, know asap. If you have an issue with the mechanics
of your vote, please contact sa-ballot@ieee.org for technical
assistance.
	
	If you are not a member of this ballot group, you can also
access the drafts at the following URLs. If you wish to offer comments
via the
	eballoting system of the SA, please send your comments to
sa-ballot@ieee.org, noting in the subject line that these comments are
for
	the P1800 Draft 4 initial ballot draft or P1364 draft 6.
	
	
http://grouper.ieee.org/groups/1800/private/IEEE-P1364-D6-LRM.pdf
	
http://grouper.ieee.org/groups/1800/private/IEEE-P1800-D4-LRM.pdf
	
	As you know, a detailed schedule and ballot process was
discussed and approved in our previous WG F2F meeting. Following is a
brief refresh: 
	

	*	02/22/05 - 03/24/05 : Ballot period. Registered entities
will send their feedback and it will be filed with the IEEE, after which
it 
		will be forwarded to me 
	*	03/28/05 : I will compile and send the accumulated
feedback, which was filed with the balloting period, to P1800 
	*	03/31/05 : Champions will complete their with their
initial classification and assignment of issues to the technical
committees. 
	*	04/12/05 : Technical committees complete their LRM
updates and issues spreadsheet updates, after which this will go back to
the Champions group 
	*	04/15/05 : Champions complete their analysis and
recommendations and forward this data to P1800 
	*	04/19/05 : P1800 WG F2F meeting in IBM Austin to approve
the changes and responses

	
	Lastly, I would like to use this opportunity to sincerely thank
all technical committees under SystemVerilog and Verilog for their hard
work
	and perseverance in accomplishing quality LRM's for both
languages. We could not have done it w/o your outstanding efforts and I
believe the whole industry, both users and EDA vendors, will benefit
from this.
	
	Best Regards,
	
	--- Johny Srouji, Chair, IEEE P1800 Work Group