Re: [sv-bc] signing in the reign

Associating signedness with distinct acts of aggregation is confusing
and could be error-prone, but it has theoretical appeal once you get
past its appearance on the page.
There isn't any good reason to stop there though: "signed logic S"
should be a variable with the values -1 and 0.  This would make

signed logic [7:0] V;  // and
logic signed [7:0] W;  // different types.

  V is an unsigned vector of signed bits
  W is a  signed vector of unsigned bits.

To a purist that's a valuable distinction.
But I wonder if it has any practical appeal, especially
since it messes with a C programmer's head?

Are you saying that P1800 is faced with resolving contradictory specs for
this feature?

Greg


Steven Sharp wrote:

> Greg Jaxon wrote:
>>I would have prefered to see the signing keyword bind tightly to
>>the nearest "{" or "[" to its right.  Somehow that option was discarded
>>during the committee work, and perhaps this is for the best.  It
>>encourages naming the datatypes which have interesting properties.
> 
> 
> The Cadence datatypes proposal to IEEE 1364 did it this way.  I consider
> it an advantage of conceptual cleanness that an arbitrary datatype could
> be declared without having to use a typedef for the intermediate types.
> 
> Most people did tend to get confused when first confronted with something
> like
> 
> logic signed [7:0] signed [1:0] [1:0] word;
> 
> They didn't understand the meaning of the signedness on the different
> ranges.  But then they might be playing with packed arrays and ask
> whether there wasn't some way to make one of the partially indexed
> values signed.  Then they would finally understand the capability that
> was provided by attaching a signedness to each range.  Perhaps the
> concept of packed dimensions is too confusing to start with, and it
> takes a while to understand that well enough to see the meaning of
> specifying signedness for different levels.
> 
> Steven Sharp
> sharp@cadence.com
> 
>