Re: [sv-bc] signing in the reign

Hi Adam,

>  >There isn't any good reason to stop there though: "signed logic S"
>  >should be a variable with the values -1 and 0. 
> 
> Yes, for the degenerate case of 1 bit, this is true, but it does
> become confusing. E.g.   some people do write:
> 
>     if (signed_bit == 1'b1) ...

The existence of one-bit signed arithmetic is not in dispute,
only our ease of writing down their types.  This expression happens
to be equivalent to signed_bit == 1'sb1, since equality does not
require the signedness of the left and right sides to conform.

>  >signed logic [7:0] V;  // and
>  >logic signed [7:0] W;  // different types.
> 
>  > V is an unsigned vector of signed bits
>  > W is a  signed vector of unsigned bits.
> 
>  >To a purist that's a valuable distinction.
> 
> That may be true but very funny.
> 
>   if (V >= 4 || V[0] == -1'b1)  -- THis seems definitely strange.

The invariance of the speed of light is also strange.

typedef logic signed [0:0] sb;
sb [7:0] V;

Yields a similarly strange data object using existing syntax.
So, at some level, anyone parsing expressions
needs to be aware of these cases.  Making them harder
to formulate syntactically is a human factors choice.
I'm trying to appreciate what leads us to prefer
languages with a bias.

As you demonstrate, making the keyword order significant
may make the language TOO sensitive.  It could also be
that by prejudicing itself toward V2K, SV is trying to
simplify the average design by lowering its bandwidth.

> Actually, doesn't bit and part selection remove the signed attribute?
> Is W[1:0] or V[1:0] signed? I haven't followed this.

Part selects are unsigned.  Ordinary selections should yield the
element type declared for the subscripted variable.

> 
>  >But I wonder if it has any practical appeal, especially
>  >since it messes with a C programmer's head?
> 
> 
> Good luck...
> 

I am not advocating one way or the other on this - just
an impartial observer of evolution in action.