The LRM is slightly self-contradictory. I think in this case, the later statements in the LRM have more authority, being more detailed and specific and the earlier ones. Specifically, 19.11.4 makes the following statements, in the following order: "SystemVerilog adds the capability to implicitly instantiate ports using a .* syntax for all ports where the instance-port name and type match the connecting variable-port name and type. This enhancement eliminates the requirement to list any port where the name and type of the connecting variable match the name and equivalent type of the instance port. This implicit port connection style is used to indicate that all port names and types match the connections where emphasis is placed only on the exception ports." "An implicit .* port connection is semantically equivalent to a default .name port connection for every port declared in the instantiated module. A named port connection can be mixed with a .* connection to override the port connection to a different expression or to leave the port unconnected." So in order for a port to be unconnected, you would have to list it specifically. Since .name does not create implicit declarations, that would be an error if it were not explicitly declared nor listed in an explicit named connection. (Note that implicit declarations from port connections only work for scalar nets, anyway.) > You wrote: > > "That means that if there is no corresponding variable or net where it was instantiated, > there would be an error." > > This is what I understood. The users would use .* to remove the tedium of specifying all > the ports that had the same name. For the cases where this is not true, or where they > required a different name they would explicitly specify the connections ala verilog 1995 > port connections. Shalom -- Shalom.Bresticker @freescale.com Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478Received on Tue Mar 22 22:52:37 2005
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