RE: [sv-bc] FW: interpretation of priority if-else or case statement

Antara,

I must disagree with Cliff on the value of the "priority" keyword.  It is
true that SIMULATION will always evaluate a case statement in the order of
case items, and an if...else...if series in the order of the if conditions.
The Verilog 1364 semantics require this for simulation.  However, synthesis
compilers can, and often do, optimize the order of these decisions, perhaps
removing all priority completely (making them parallel evaluations.  The
priority keyword clearly documents that the designer expects a multiple
branch decision to be evaluated in a specific order.  This documentation is
more than a comment, it is part of the language.  Synthesis and formal
verification tools can utilize the priority keyword to ensure that the
designer's intent is realized in implementation.  I feel "priority" is both
valuable, essential, and an appropriate choice of keywords.

Just my opinion...

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland                      Sutherland HDL, Inc.
stuart@sutherland-hdl.com              22805 SW 92nd Place
+1-503-692-0898                        Tualatin, OR 97062

Training engineers to be Verilog and SystemVerilog wizards!
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> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On 
> Behalf Of Clifford E. Cummings
> Sent: Tuesday, March 29, 2005 7:59 AM
> To: antarag@interrasystems.com
> Cc: sv-bc@eda.org
> Subject: Re: [sv-bc] FW: interpretation of priority if-else 
> or case statement
> 
> Hi, Antara -
> 
> You are correct that case statements and if-else-if 
> statements are already priority. I noted in section 4.1 of a 
> recent conference paper (read the section for my full 
> argument) that I really dislike the keyword "priority" 
> because it is confusing
> 
> http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_S
> ystemVerilog_UniquePriority.pdf
> 
> What priority case offers is run-time checking to see if the 
> case expression matches one of the defined case items. In 
> essence, by adding the priority keyword, you have said that 
> the case statement defines all possible cases; hence, a 
> better keyword would have been "full," "fullcase," 
> or "all_possible," but alas, we are now stuck with the 
> confusing "priority."
> 
> If during simulation or if a formal tool can prove that it is 
> possible to find a case expression that does not match one of 
> the case items, then you have violated the assertion that all 
> possible cases have been defined in the case statement (or 
> if-else-if statement) and accord to the P1800 standard a 
> warning is issued (according to the SV 3.1a standard it was 
> an error - I have noted this in my ballot comments - when an 
> assertion fails, and "priority" really is an assertion, it 
> should be an error, and the SNUG San Jose conference 
> attendees also raised this point).
> 
> Also note that either adding a "default" to a case statement 
> or a final "else" to an if-else-if statement will nullify the 
> "priority" keyword because you have now said, "and for ALL 
> other cases, do the following."
> 
> I don't like the "priority" keyword, but we are now stuck 
> with it. Just think of it as an engineer stating the 
> assertion that all possible cases of else-if's have been 
> defined. The paper above gives many examples and details.
> 
> Hope this helps.
> 
> Regards - Cliff
> 
> At 10:22 PM 3/28/2005, Maidment, Matthew R wrote:
> > >From: Antara Ghosh <antarag@interrasystems.com>
> > >To: sv-bc@server.eda.org
> > >Subject: interpreation of priority if-else or case statement
> > >
> > >Hello,
> > >
> > >What is the difference between the behavior of priority 
> if-else/case 
> > >statement and normal (without unique or priority 
> attribute) if-else 
> > >statement?
> > >
> > >LRM states "A priority if indicates that a series of if ...
> > >else ... if
> > >conditions shall be evaluated in the order listed." But 
> that is the 
> > >inherent behavior of an if-else if statements. The only difference 
> > >between normal if and priority if seems to be the fact 
> that the later 
> > >errors out if there is a condition which is not present in if-else 
> > >ladder.
> > >Please let me know if I am missing something.
> > >
> > >Thanks
> > >Antara Ghosh
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com Expert 
> Verilog, SystemVerilog, Synthesis and Verification Training
> 
> 
> 
>