[sv-bc] Efficiency issue with erratum 578

While it has been assumed that an input or output port with an explicit data
type would always be a variable, I have some concerns about the simulation
efficiency of requiring that as the default.  Variables require inserting a
continuous assignment for each port connection.  When a value was passed
through multiple levels of hierarchy, a continuous assignment would be
required at each level.  This is extremely inefficient.

In Verilog, where ports defaulted to nets, this inefficiency was eliminated
because net ports can be collapsed.  This has always been an important
optimization for simulation performance.  I don't think we want to require
slow simulation just because someone declares a port with a data type.

In many situations in SystemVerilog, you can't tell from within the design
whether a port has been treated as a variable or a net (especially if you
set your default net type to uwire).  I think it is important for simulation
performance that we allow implementations to use a net in these situations,
so that ports can be collapsed.

One of the ways that this does affect the design is that port collapsing
will "fix" incorrect port directions as a side effect.  This is probably a
desirable effect.

As a result, I am going to modify my proposal for erratum 578 to allow an
implementation to default ports with a data type and no port kind to be a
net instead of a variable, if the data type is allowed for a net and there
are no procedural assignments to it.  This should have almost no visible
effect on behavior, but allow more efficient simulation.

Steven Sharp
sharp@cadence.com