Re: [sv-bc] Re: issue 324 for asymmetric casex

This proposal allows only ranges in the case items.  This is incorrect.
It is supposed to allow values, with x/z treated as wildcards.  That is
the primary reason for adding this.  Ranges are just a further enhancement.
Note that the sets for the inside operator allow values as well as
ranges.

I have a problem with changing the case expression to be self-determined
for a "case inside".  This means that if you change an existing casex to
a case inside, the behavior may change because of the change in evaluation
sizes.  The desire was for _only_ the wildcard treatment to change.

I looked at the inside operator to see how the sizes are defined.  It turns
out that this is not specified at all.  This is another hole in the LRM.

Note that evaluating something self-determined and then trying to apply
an operation that requires equal sizes (such as a compare), is not
consistent with Verilog expression size rules.  The rules for
context-determination are specifically designed so that any sub-expressions
being combined are already of the correct sizes.

Without ranges, this should clearly work like other cases.  There is a
single size determined from all of the expressions, and that size is used
in evaluating all expressions.  With ranges, the most consistent extension
would be to include the left and right expressions of the ranges in the
context.

Steven Sharp
sharp@cadence.com