Re: [sv-bc] Re: issue 324 for asymmetric casex

I would like to withdraw this proposal entirely, and see if we can't
put together something that would do a better job of avoiding mismatches.
The inside operator doesn't seem to be the right one for the job.

I need to think it through more, but perhaps an asymetric case-wildcard
as proposed earlier (with no ranges) except that

    1) The case items must be literals

    2) An x or z in a case item would match only a 0 or 1 in the
       case expression.

That is, a don't-care in the case item would mean I don't care if the
case expression has a 0 or 1 in that bit, but it must be an actual bit,
not an x or z.

>The original reason for adding this functionality is to provide a version
>of casex that won't produce pre/post-synthesis simulation mismatches.  The
>description should make that part of the functionality clear.

-- Brad