Hello Adam That would be rather dangerous. Furthermore in general this will not work for connection between modules, even if the nets existed, since in general there are often naming schemes on the port names, so in module A you have a port data_out and in module B you have a port data_in. The .* notation will not handle such intermodule connections as even for explicit nets there can be nothing that matches both ends of the connection. This problem is more obvious in a datapath application, i.e. a chain of several modules handling red/green/blue data for graphics, compared to a processor application with address/data/control. Since in the former case we are talking about different but similar connection types whereas the latter case the connections are common to all modules. i.e. point to point vs star/broadcast. The .* connection is intended more for instantiating a DUT/DUV module in a testshell. To handle the scenarios I describe for inter module connections, constructs similar to regular expressions would be required - as a future enhancement someday. Not implict nets. Note so far only scalar nets were ever implicit in Verilog - but only if explicitly connected, not for .*. Regards Jonathan Bradford Adam Krolnik wrote: > > > Hi Steven; > > > that .* will not implicitly declare nets. > > It is unfortunate that nets have to be declared for .* to have its > desired effect. > I would be nice to be able to add ports between two modules and have > them become > connected without having to modify the parent module that instantiates > them. > > Maybe a future enhancement someday. > > -- Jonathan Bradford CAD Engineer Phone +49 (0)761 517 2884 Fax +49 (0)761 517 2880 mailto:jonathan.bradford@micronas.com MICRONAS GmbH Hans-Bunte-Str.19 D-79108 Freiburg Germany http://www.micronas.comReceived on Wed Apr 6 09:31:01 2005
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