Re: [sv-bc] Issue 548: .* and implicit nets

>I would be nice to be able to add ports between two modules and have them 
become
>connected without having to modify the parent module that instantiates them.

Note that this would only work for 1-bit ports anyway, as implicit nets
created for port instantiations are always scalars.


>Maybe a future enhancement someday.

My concern would be that this much implicitness would be error-prone.
Normally you have either the declarations in the parent module (for .*)
or the explicit port expressions (for implicit nets), which gives some
idea of the intended connections.  If something doesn't match, there is
a chance to catch it and produce an error.

With nothing explicitly specified by the user, the implicit rules are
guessing what the user wants, with nothing to check against.  For example,
if you thought two modules had matching port names, but they don't, you
wouldn't get any errors.  Each would create implicit nets for each of
its ports, which would satisfy the requirements for .* connections, but
the nets wouldn't connect the two instances.

I asked a little while ago whether .* was allowed to leave ports
unconnected if there was no appropriately named net/variable in the
parent.  I was told that it could not, and that this was a safety issue.
But if you create implicit nets for .* ports, you have effectively
allowed this, at least for 1-bit ports.  Any otherwise unconnected
port would create an implicit net.  But if that implicit net is not
connected to anything else, this is the same as leaving the port
unconnected.  There would be no error to tell you this happened.

Steven Sharp
sharp@cadence.com