Re: [sv-bc] Assignment pattern lvals (mantis 623)

Gord,

Regarding your ref and inout issues, recall that the definition of
assignment-like context excludes module inout and ref port connections,
as well as function ref port passing.  So an (untyped) assignment pattern
could not be used as even the right-hand side in those places.

I think it might address your issues about ref ports and inout
ports then to say that, moreover, even a (typed) assignment pattern
expression is illegal outside of an assignment-like context.
(That is not to say that they could only be used *as* the
left- or right-hand side of such a context, but just only *within*
them.)

At least the rule would be easy to remember -- you can use
assignment pattern expressions only in an assignment-like context.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
Gordon Vreugdenhil
Sent: Tuesday, April 12, 2005 12:23 PM
To: SV_BC List
Subject: [sv-bc] Assignment pattern lvals (mantis 623)


Issue 2

Can assignment pattern expressions be actuals to
ref parameters or ref ports?  This is not specified
in the current text.


Issue 4

The current behavioral description is completely inadequate
for inout port connections.  Since the behavioral
description has the implication of the "var" intermediate
as noted in Issue 4, the most consistent view would be
to disallow assignment patterns for inout ports in the
same manner in which vars are disallowed.