Cliff, If you read http://www.boyd.com/1364_btf/report/full_pr/350.html, you will have a good historical review on the config discussion, which appears to have started to be replayed again. And, I stand by my comments in May 2004 that restrictions on the placement of configs as being suggested is a regression from the 1364-2001 spec and does not serve the user. But I would support whatever cleanup is desired for semicolons. -Dennis -----Original Message----- From: owner-etf@boyd.com [mailto:owner-etf@boyd.com] On Behalf Of Clifford E. Cummings Sent: Wednesday, April 20, 2005 10:55 PM To: btf@boyd.com; etf@boyd.com; sv-bc@eda.org; sv-ec@eda.org Subject: Re: Configs Intent - was: potential command line option Hi, Brad - Was this discussed and approved in committee meetings? (I missed a large number of meetings and could have missed this discussion). I would prefer required semicolons as originally intended and just fix all my errors in the config section as previously noted. Regards - Cliff At 08:58 PM 4/20/2005, Brad Pierce wrote: >In SystemVerilog these semicolons are optional. > > http://www.eda.org/sv/Changes_draft6/LRM_Changes_A_BNF.html > >-- Brad > >-----Original Message----- >From: owner-btf@boyd.com [mailto:owner-btf@boyd.com]On Behalf Of >Shalom.Bresticker@freescale.com >Sent: Wednesday, April 20, 2005 8:22 PM >To: Clifford E. Cummings >Cc: btf@boyd.com; etf@boyd.com; sv-bc@eda.org; sv-ec@eda.org >Subject: Re: Configs Intent - was: potential command line option > > >Regarding the semicolons at the end of the statements, there is already >an ETF issue on this. In fact, I think there are two. I think there is >one issue (# 372 ?), which lists this as one of several config issues, >and I think there is another one ( 5xx ? 501 ?) which is dedicated to >this issue. > >Shalom ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification TrainingReceived on Wed Apr 20 23:16:59 2005
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