[sv-bc] Fwd: AW: Ballot feedback feedback

Feedback from the entity describing the bind issue:


>One example is shown attached. Here, a type
>is declared in a module (here i_t3). In this module, a new type, call "new_type"
>is declared.
> 
>Another module (i_x_t3) is bound to that module and uses the declared type
>"new_type". An applicaiton example would be to sample that value for a later
>check with an assertion.
> 
>As far as I remember, SystemVerilog requires, that a type must be declared before
>its use. 
> 
>Now to the example: Assume, the bound module i_x_t3 is handeled like a
>nested module at the end of module i_t3, then the new_type is declared
>before, and is known to i_x_t3.
> 
>Assume however, that the i_x_t3 is handeled like a nested module inserted at
>the beginning of the module, then type new_type is not declared at that
>place. An error should be reported in that case.
> 
>To make this clear, I recommend, to define in the LRM, at which place a bound
>module is inserted, and how the compile order of the bind statement influences
>the place, the bound modules (in case there are more than one) are inserted.
> 
> 
>
>//==========================================================
>
>bind i_t3 i_x_t3 i_x_t3_inst(tmp);
>
>//========================================================
>
>module i_t3 (output logic y, input bit a);
>
>typedef new_type logic[1];
>
>new_type tmp;
>
><mailto:always@(y>always@(y)
>
>tmp[0] = a; 
>
>y<=(!tmp[0]);
>
>end
>
>endmodule
>
>//========================================================
>
>module i_x_t3 (input new_type x);
>
>new_type y;
>
><mailto:always@(x>always@(x)
>
>begin
>
>  y = x;
>
>   assert y = !x;
>
>end
>
>endmodule 
> 
> 
> 
> 

My letter requesting feedback:

>        In the SV-BC, we are discussing one of your items: 
>"bind" statement needs clarification according to the place the bound module, interface, program is bound to. As an example: There is a program p with a type pt. Another program jap is bound to that program p, and uses the declared type pt. This is only valid, if the type declaration is analysed first, i.e. the jap program is "inserted" at the end of program p. Similarly, it must be specified, how a set of bind statements is analysed. 
>In the SV-BC, we believe that the ordering of bind statements is immaterial to understanding a design.  Can you provide an example that demonstrates that this isn't so?
>
>The committee has added language that defines that the bind statements are analyzed at the end of the module.  The proposal can be found as added blue text in the attached html file on:
>
>http://www.eda.org/svdb/bug_view_page.php?bug_id=0000627
>The file:  http://www.eda.org/svdb/file_download.php?file_id=789&type=bug
>
>We'd appreciate your insights if you see additional issues.
>
>Thanks,
>
>Karen