Re: [sv-bc] Keywords

From: Clifford E. Cummings <cliffc_at_.....>
Date: Tue Apr 26 2005 - 08:41:23 PDT
Hi, Kev -

I think all the vendors could do as you have suggested, but most if not all 
would prefer to have a single list of keywords.

Turns out, the biggest offender is the keyword "config," which is the one 
we need to descend into the next level of keywords.  Cadence implemented 
most of Verilog-2001 and then got around to implementing configs. Now they 
have the problem of customers using all types of Verilog-2001 capabilities, 
but some of the Verilog-2001 code uses "config" as an identifier, so it is 
not as easy as telling the tool that this block of code is Verilog-1995, as 
I suggested in an earlier email message.

One lesson to be learned from this is to create tools that flag all 
keywords as un-implemented features so engineers don't start using some 
keywords and later discover that additional keywords were reserved but it 
is now difficult to separate new features from recently implemented features.

Regards - Cliff

At 12:02 AM 4/26/2005, you wrote:
>Just as a matter of interest: whose compilers can't handle limited context 
>keywords?
>
>I usually write recursive descent parsers that can handle tokens being 
>keywords or
>not depending on context. It seems that life would be easier if "keyword 
>status"
>could be limited to particular scopes for particular words e.g. there is 
>no good
>reason that keywords for configuration should have any special meaning 
>outside of
>a config block.
>
>Kev.

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Tue Apr 26 08:45:51 2005

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