Re: [sv-bc] Keywords

Paul Graham wrote:

>> From previous e-mails it looks to me like "config" is a top-level block 
>>(don't have an LRM handy), in which case there is no reason to recognise 
>>"config" as a keyword in a module.
>>    
>>
>
>Of course that would make it impossible for a future version
>of verilog to allow a configuration to be nested within a
>module.  To take an example from vhdl, it would have been
>possible for the '87 lrm to allow the keywords 'entity' and
>'configuration' to be used as identifiers within an
>architecture.  But that would have prevented the '93
>extensions of entity and configuration instantiations.
>
>Flexibility in the use of keywords can get very complicated,
>unless you take the approach used in lisp-like languages,
>where there are very few predefined lexical elements and
>most keyword-like constructs are only recognized at the
>beginning of a list.
>
>Paul
>  
>
I think you could probably come up with a syntax that would be backward 
compatible
and had limited scope e.g. just labeling the block might be sufficient 
to disambiguate -

       module foo;

          my_config: config ...
//or
          local config ...                  // local can be a globally 
reserved keyword

So I think "impossible" is too strong a word. Also, I generally avoid 
VHDL when looking
for examples on how to do (user-friendly) things :-)

Kev.