Re: [sv-bc] Keywords

Paul Graham wrote:

>>Nor is there any reason to recognize "module" as a keyword in a module.
>>But for the sake of uniformity, it is sacrificed.
>>    
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>Well there is, if you allow nested modules.
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>>When they do, perhaps one lesson to learn from the "config" experience
>>should be to give words a decent english spelling, e.g., "configure" or
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>Nobody's complaining about 'endgenerate'.  But keywords like
>'bit' and 'byte' will be a problem for some existing designs.
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>Paul
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bit and byte don't have to be considered keywords at all: they can be 
redefined as (optional) pre-defined types (typedefs from something less 
likely to clash - http://www.eda.org/sv-bc/hm/0838.html).

logic is a similar problem for existing Verilog-AMS users who want to 
migrate into SystemVerilog-AMS.

Note: this is in the Issue List, but is marked closed -

 http://www.eda.org/sv-bc/display_3.1a_issue.cgi?issue_num=38

- IMO it shouldn't be marked closed until there is actually an approved 
alternative solution, and it's not clear to me how exactly namespaces 
would fix the problem.

Kev.