RE: [sv-bc] Small issue with array type rules

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Mark
> Hartoog
> Sent: Thursday, April 28, 2005 8:06 AM
> To: Vreugdenhil, Gordon; 'SV_BC List'
> Subject: RE: [sv-bc] Small issue with array type rules
> 
> Gordon Vreugdenhil:
> >
> > In 5.2 we have:
> >     SystemVerilog accepts a single number, as an alternative to a
> >     range, to specify the size of an unpacked array, like C. That
> >     is, [size] becomes the same as [0:size-1].
> >
> > This doesn't specify whether it is an error if size <= 0.  I
> > think that was likely the intent, but since Verilog ranges
> > can go in either direction, [0:size-1] is valid for any value
> > of size.  Does anyone know whether non-positive values were
> > intended to be allowed?  The text above doesn't actually make
> > it an error.
> 
> I have seen this issue also. I think the intent was that size was
> positive. For example, [0] becomes [0:-1], which is actually 2
elements.
> I find that a rather surprising.
> 
> Note, however, that size is a constant expression, so you cannot
> determine this until after elaboration.
> 
> Since this was not a ballot issue, can we fix this?

[DR>] 
[DR>] Maybe by delivering a few pizzas to Stu's house. :)
>