Re: [sv-bc] Keywords

Putting library, configuration, and module syntax in a single file 
should be fine. (and possibly quite useful when sending test cases to a 
library vendor - so you can easily point to the library cells that are 
problematic)   But remember that it is forbidden to read additional 
library statements once the first module has been bound.

  If you are going along these lines, you might want to think about the 
ability to directly specify the library in a module declaration:
    module rtlLib.foo ();
Currently all streamed in modules would be forced into the 'work' library.

>3. Grammar allowed.  We could allow the full library map syntax in Verilog
>   source files or just configs.  If we only allow configs, do we stop
>   reserving the library map keywords in Verilog source?
>
>Steven Sharp
>sharp@cadence.com
>  
>