[sv-bc] Parameterizing functions using classes -- ballot issue 225

In Verilog, the effect of a parameterized function can be achieved by
declaring it within a parameterized module, instantiating the module
as needed and calling the function via a hierarchical name.

In SystemVerilog, it's more convenient to get this effect instead
by declaring the function within a parameterized class (see 12.23).

For example,

     a = f#(33,type(int))(x,y) + pkg::g#(22)(z);

can be implemented as

     begin
       var f_class#(33,type(int)) f_dummy = new;
       var pkg::g_class#(22) g_dummy = new;
       a = f_dummy.f(x,y) + g_dummy(z);
     end

I don't think that the syntax proposed for ballot issue 225 adds any new
functionality to SystemVerilog.

    http://www.eda.org/svdb/bug_view_page.php?bug_id=696

Probably the current proposal is too restrictive semantically.  Although
it's correct that parameterized subroutines, like subroutines declared as
class
methods, should be automatic by default, there would be no harm in allowing
them to be explicitly declared static, as can already be done with class
methods.

-- Brad