RE: [sv-bc] Naming of unnamed sequential blocks

According to 9.8, only named blocks create a new hierarchical scope.

So it would be foo.f2.channel.

You wouldn't want the hierarchical path to be dependant on whether or
not a variable was declared in the unnamed block, would you?

Dave

P.S. How's that SystemVerilog emacs mode coming along? :)


> 
>  As it is, what happens if there are named blocks with variable
>  declarations in the unnamed block that has a declaration? What is the
>  path to those variables?
> 
>  module foo;
>  ...
>  always @(a or b or c) begin // no name so I can have a local variable
>     reg [31:0] mysecret; // magically hidden name because begin is not
> 			 // named
>     mysecret = $random;
>     fork
>       begin : f1
>         wait #1000 disable f2;
>       end
>       begin : f2
>         reg [3:0] channel;
> 	pid = $random(0,5);
> 	data = fetch_data(pid, mysecret);
> 	disable f1;
>       end
>     join
>  end
> 
>  is it foo.f2.channel, or foo.unamed_block1.f2.channel??  Or are these
>  also hidden?  That would be a change because in 1364 these would be
>  foo.f2.channel
>