Re: [sv-bc] Function in generate block

I think this syntax is not legal under verilog-2005.
I think the generate_block (begin...end) is only
allowed under an if/else, for-loop, or case generate construct.

However, under Verilog-2001, I think no scope would be created
and the function would exist in the outer module scope, and
therefore it would be ok.

Shalom

On Wed, 25 May 2005, Greg Jaxon wrote:

> Just offering a personal opinion based on no research...
> Take away the generate/endgenerate pair.
> You're left with a block that declares a function and
> then closes without calling it. In any classically
> scoped language this makes the function identifier
> undefined in the subsequent always block.
> 
> In V2K certain blocks inside generate vanished (i.e.
> did not delimit new scopes) if they were controlled by
> constructs that can be fully resolved at generate-time.
> 
> An outer begin/end probably vanishes in V2K, and should
> not vanish under generate2005 rules.
> 
> Rakesh Gulati wrote:
> > module test(clk,reset,a,b,c,x,y,z);
> > 
> > parameter SIZE = 4;
> > input     clk;
> > input     reset;
> > input     [SIZE-1:0] a;
> > input     [SIZE-1:0] b;
> > input     [SIZE-1:0] c;
> > output    [SIZE-1:0] x;
> > output    [SIZE-1:0] y;
> > output    [SIZE-1:0] z;
> > reg       [SIZE-1:0] x;
> > reg       [SIZE-1:0] y;
> > reg       [SIZE-1:0] z
> > generate
> > begin
> >  function [SIZE-1:0] output_assign;
> >    input [SIZE-1:0] in;
> >    output_assign = !in;
> >  endfunction
> > end
> > endgenerate
> > 
> > always@(a or b or c)
> > begin
> >  x = output_assign(a);
> >  y = output_assign(b);
> >  z = output_assign(c);
> > end
> > 
> > endmodule
> > 
> > 
> > Function output_assign defined inside the generate block, but used 
> > outside in procedural block.  Is this a  semantic error at the place of 
> > function call in SV as the function is in unnamed block name space ? In 
> > my opinion in V2k this is a pass case.
> > 
> > Rakesh
> > 
> > 
> > 
> > 
> 
> 

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