RE: [sv-ec] RE: [sv-bc] Is this a valid syntax

I really doubt there is any pro-active decision making going on here. 

I would have assumed the base type to be bit or 2-state, not 4-state,
since the implicit type of an enum is an int. That's why this feature
was removed in the first place, it wasn't clear what the base type
should be.

That's why we spend our time working on standards.

Dave


> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Friday, July 01, 2005 1:17 PM
> To: kausikd@cal.interrasystems.com; sv-ec@eda.org; sv-bc@eda.org;
Rich,
> Dave
> Subject: Re: [sv-ec] RE: [sv-bc] Is this a valid syntax
> 
> 
> >This is old syntax that was removed in SV3.1a. You are probably using
a
> >simulator that is not up to date.
> 
> Or one whose implementors decided this was an obvious extension that
> should be allowed.  I don't see any problem with this syntax assuming
> a base type of logic, as happens in similar declarations elsewhere in
> Verilog.
> 
> Steven Sharp
> sharp@cadence.com