RE: [sv-bc] Is an unnamed block with declarations a scope?

Mac's reply was bounced. 

>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] 
>Sent: Thursday, August 11, 2005 7:57 AM
>Subject: BOUNCE sv-bc@eda.org: Non-member submission from 
>["Michael McNamara" <mcnamara@cadence.com>] 
>
>Subject: RE: [sv-bc] Is an unnamed block with declarations a scope?
>Date: Thu, 11 Aug 2005 07:56:50 -0700
>
>I go back to my point that we should remove unnamed blocks.  
>They add no value and only break things; and as you point out 
>the problem is even worse than first surmised.
>
>-mac
>
> -----Original Message-----
>From: 	Gordon Vreugdenhil [mailto:gordonv@model.com]
>Sent:	Thu Aug 11 07:30:15 2005
>To:	SV_BC List
>Subject:	[sv-bc] Is an unnamed block with declarations a scope?
>
>I'd like to get people's input as to the interpretation of an 
>unnamed block being a scope.  The key paragraph in P1800 
>(latest draft) Section 6.6 is:
>
>     In SystemVerilog, data can be declared in unnamed blocks as
>     well as in named blocks. This data is visible to the unnamed
>     block and any nested blocks below it. Hierarchical references
>     cannot be used to access this data by name.
>
>This doesn't say that an unnamed block is a scope (which is a 
>good thing).  Consider the following:
>
>    module top;
>      initial begin
>          begin:A
>             $display("hello");
>          end
>      end
>      initial begin
>          begin:A
>             $display("hello");
>          end
>      end
>    endmodule
>
>In 1364, this is an error since the block name "A" is created 
>in the module scope causing the second block to conflict.
>
>Question 1: is this also illegal under P1800?
>
>Question 2: if I change the first initial block to be:
>      initial begin
>          reg x;
>          begin:A
>             $display("hello");
>          end
>      end
>
>What is the scoping of the name "A"?  Is it hidden inside an 
>unnamed scope or is just the name "x" hidden since it is the 
>only data declaration?
>
>
>If "A" is in an unnamed scope in the second example and is in 
>the module scope with the original example, does this imply 
>that an unnamed block changes from not being a scope to being 
>a scope when you have a declaration present?
>
>Strictly reading the LRM, only a "data declaration" is hidden.
>What happens to types?
>
>Given the grammar rule:
>     seq_block ::=
>         begin [ : block_identifier ]
>            { block_item_declaration }
>            { statement_or_null }
>         end [ : block_identifier ]
>
>from the LRM, one option is that unnamed blocks whose 
>"block_item_declaration" list is empty are not scopes while 
>those whose "block_item_declaration" list is non-empty are scopes.
>
>The implication here is that nested named blocks are not 
>hierarchically referencable if they are in an unnamed block 
>with block_item_declaration items but are otherwise.  This 
>preserves 1364 visibility but does mean that adding a simple 
>data declaration in an unnamed block can impact visibility of 
>nested named blocks.
>
>Another option would be to say that for unnamed blocks only 
>the "block_item_declaration" items are hidden; statement 
>labels and/or nested block names in the statement would exist 
>in the nearest upwards named scope.
>This causes an irregularity in the handling of the names that 
>is very counter intuitive.
>
>
>So, any opinions on this?
>
>Gord.
>--
>--------------------------------------------------------------------
>Gordon Vreugdenhil                                503-685-0808
>Model Technology (Mentor Graphics)                gordonv@model.com
>
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