Re: [sv-bc] clarification on rules for enums

>From: "Brad Pierce" <Brad.Pierce@synopsys.com>

>>What matters is whether the value specified fits into the enum, not
>what expression was used to specify the value.
>
>But I don't know what it means for a value to "fit".  Shouldn't the
>constant expression instead be evaluated in the context of an assignment
>to a localparam of the given base type?

That would certainly have been a more Verilog-like way to define it:
follow the existing rules for assignment, with their implicit type
conversions.  But that isn't what got put into the standard here.

I think most of us have a reasonable intuitive idea of what is meant
by "fit".  The problem is putting it into formal terms.

I think you need to evaluate the expression in the context of an
assignment to the base type (in case there is any widening involved).
But if the assignment ends up causing a truncation instead, and that
truncation loses significant bits, then the value didn't "fit".

This gets less clear when you start dealing with signed values.  There
are generally different rules for what are considered unsigned and signed
overflow (truncating non-zero bits for unsigned, and truncating bits that
don't match the final sign bit for signed).  But do you use the signedness
of the enum type or the signedness of the expression?  If you declare a
signed enum type, and assign an unsigned value that will be treated as
negative in the enum type, was that an overflow?  What if you assign a
negative signed value to an unsigned enum type?

Steven Sharp
sharp@cadence.com