[sv-bc] Re: [sv-ec] Conflict in Tagged Union expression

Sarmistha,

I agree that the intent was probably

     tagged_union_expression ::= tagged member_identifier [ primary ]

This is really an SV-BC issue, not an SV-EC issue, so I'm adding its
reflector  to the distribution.

-- Brad

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Sarmistha Bhattacharya
Sent: Tuesday, September 20, 2005 10:39 PM
To: sv-ec@eda.org
Subject: [sv-ec] Conflict in Tagged Union expression 

Hi,
The LRM says tagged union expressions are part of expression :
(Ref :  SV-3.1a   LRM,  Page  495)

expression ::=
| tagged_union_expression

And, tagged union expressions are defined as :
(Ref :  SV-3.1a   LRM,  Page  495)

tagged_union_expression ::= tagged member_identifier [ expression ]

Consider the following situation :
////////////////////////////////////////////
int a=0, b=1;
union tagged {
      int y;
       .. } x;

initial
 begin
    x = tagged y a + b;   //  -> parser conflict
    ..
 end
///////////////////////////////////////////

The conflict arises because according rule, 'tagged y a' itself can be a
tagged union expression, and since there is no delimiter, the parser
does not understand whether to reduce it here, or shift further to get
'tagged y a + b' as the whole tagged union expression .

In the LRM, in all the examples, a bracket has been used for the
expression part.
( Ref :  SV-3.1a   LRM,  Page 85 )

vi1 = tagged Valid (23+34);

Could someone please tell me if the bracket has been missed out , or i
am missing something here.
Thanks,
-sarmistha.