RE: [sv-bc] Ambiguous declaration / initialization in for-loop

>From: "Michael Mac McNamara" <mcnamara@cadence.com>

>However, the text Chris quotes seems to require this, implying a
>compliant tool must reject code where some variable not declared in the
>for loop is read or written in the calculation of the control of the
>loop.

The term "loop control variable" was a poor choice, given the
flexibility allowed in Verilog for-loops, where the variables
that are initialized may or may not be the same variables that
are tested or incremented elsewhere in the loop control.

I think we can resolve your concerns by interpreting "loop control
variables" as only the variables initialized in the initialization part
of the for-loop construct.  No other variables are considered to be
"loop control variables", even if they are referenced in the condition
or increment parts of the for-loop construct.  And conversely, there
is no requirement that "loop control variables" be referenced in the
condition or increment parts of the for-loop construct.

In the absence of any new restrictions, these variables would follow
the same rules as any other variable in Verilog.  Their scope is
local to the for-loop (essentially an unnamed block surrounding the
for-loop construct, as Brad indicated).  You can read them inside the
loop body.  You can write them inside the loop body (though this is
probably bad practice).  You can't reference them from outside the
loop body using a hierarchical reference, since they are specified
to be automatic variables.

Steven Sharp
sharp@cadence.com