Yes, along with procedural continuous assignments. Just reading Shalom's post: I stand by my statement that they are not to be used other than to support legacy code. Their interaction with new SystemVerilog constructs has not been defined. The line between "possible deprecation" and "actual deprecation" is opinionated. The 1364-2005 LRM "actually" deprecated the ACC/TF PLI routines. That means someone could build a simulator and claim to be Verilog compliant without implementing the ACC/TF routines. In reality, that's not going to happen for awhile. If I knew that the 1364 was going to actually deprecate the ACC/TF routines, I would pushed harder to the actually deprecate defparam. Dave > -----Original Message----- > From: Premduth Vidyanandan [mailto:premduth.vidyanandan@xilinx.com] > Sent: Monday, November 07, 2005 8:15 AM > To: Rich, Dave; francoise martinolle; Surya Pratik Saha; sv-bc@eda.org > Subject: RE: [sv-bc] Defparam on member of parameter struct > > Hi Dave, > > Just to understand what you are saying. Defparams are deprecated for > Systemverilog correct? It is not deprecated for Verilog itself? > > Is that correct? > > I think the answer is yes, although wanted to check. > > Thanks > Duth > > > -----Original Message----- > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of > Rich, Dave > Sent: Monday, November 07, 2005 9:08 AM > To: francoise martinolle; Surya Pratik Saha; sv-bc@eda.org > Subject: RE: [sv-bc] Defparam on member of parameter struct > > And the reason it is not allowed is because the defparam statement has > been deprecated. Deprecated means that the feature has been removed from > the standard, and should not be used other to support legacy code. > > Dave > > > > -----Original Message----- > > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of > > francoise martinolle > > Sent: Monday, November 07, 2005 7:53 AM > > To: 'Surya Pratik Saha'; sv-bc@eda.org > > Subject: RE: [sv-bc] Defparam on member of parameter struct > > > > I do not think it should be allowed. > > > > -----Original Message----- > > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of > Surya > > Pratik Saha > > Sent: Monday, November 07, 2005 6:04 AM > > To: sv-bc@eda.org > > Subject: [sv-bc] Defparam on member of parameter struct > > > > Hi, > > In System Verilog, we can declare a paremeter as struct. > > > > As per V2K LRM, a defparam can be applied on parameter only. > > > > So can a defparam be applied on a member of struct param? > > > > Is the following test case is valid? > > > > module top; > > parameter struct {int x;} p = {1}; > > defparam p.x = 1; > > endmodule > > > > Regards > > Surya. > > > > >Received on Mon Nov 7 08:45:04 2005
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