Re: [sv-bc] Defparam on member of parameter struct

At 12:25 PM 11/8/2005, Brad Pierce wrote:
>When the function is `included, then the following rewriting doesn't
>work.
>
>-- Brad

It worked for me (although I am not a great fan of most `include code in 
Verilog-2001 because often included code, like tasks and functions, could 
not be tested with separate compilation - SV packages are better).

This following worked for me:

FILE: fun_inc.v

module top;
   foo #(.p(5)) f();
endmodule

module foo #(parameter p = 3);
   integer i;

   initial i = fun(1'b0);

   `include "fun.v"
endmodule

FILE: fun.v

   function fun;
      input in;
      $display("In fun, p = %0d", p);
   endfunction

Regards - Cliff

> >>module foo;
> >>   function fun;
> >>      input in;
> >>      parameter p = 3;
> >>      $display("In fun, p = ", p);
> >>   endfunction // fun
> >>   integer      i;
> >>   initial i = fun(1'b0);
> >>endmodule // foo
> >
> >Easily modified to avoid the defparam as follows:
> >
> >module top;
> >   foo #(.p(5)) f();
> >endmodule
> >
> >module foo #(parameter p = 3);
> >   integer i;
> >
> >   initial i = fun(1'b0);
> >
> >   function fun;
> >      input in;
> >      $display("In fun, p = %0d", p);
> >   endfunction
> >endmodule

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Cliff Cummings - Sunburst Design, Inc.
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