Re: [sv-bc] Defparam on member of parameter struct

Sorry, here's what I meant --

"fun_inc.v"
-----------
   task rotl;
     parameter M = 8;
     input [M-1:0] in;
     input [31:0] n;
     output [M-1:0] out;
     reg [M-1:0] temp;
       {out,temp} = {in,in} << n ;
   endtask 

"test.v"
-----------
   module test(in,out);
     parameter N = 16;
     input [N-1:0] in;
     output [N-1:0] out;
     reg [N-1:0] out;
     always @(in) begin
       rotl(in,3,out);
     end
     `include "fun_inc.v"
     defparam rotl.M = N;
   endmodule

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Tuesday, November 08, 2005 2:33 PM
To: sv-bc@eda.org
Subject: Re: [sv-bc] Defparam on member of parameter struct

The no-defparam style makes the included function more context-sensitive
and requires the calling module to have a parameter with the same name
as that of the function.

Here's a Verilog-1995 example that avoids that by using a defparam.

"fun_inc.v"
-----------
    task rotl;
     parameter rotl_N = 8;
     input [N-1:0] in;
     input [31:0] n;
     output [N-1:0] out;
     reg [N-1:0] temp;
       {out,temp} = {in,in} << n ;
    endtask 


"test.v"
------------
   module test(in,out);
     parameter N = 16;
     input [N-1:0] in;
     output [N-1:0] out;
     reg [N-1:0] out;
     always @(in) begin
       rotl(in,3,out);
     end
     `include "fun_inc.v"
     defparam rotl.rotl_N = N;
   endmodule

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Clifford E. Cummings
Sent: Tuesday, November 08, 2005 1:39 PM
To: sv-bc@eda.org
Subject: Re: [sv-bc] Defparam on member of parameter struct

At 12:25 PM 11/8/2005, Brad Pierce wrote:
>When the function is `included, then the following rewriting doesn't 
>work.
>
>-- Brad

It worked for me (although I am not a great fan of most `include code in
Verilog-2001 because often included code, like tasks and functions,
could not be tested with separate compilation - SV packages are better).

This following worked for me:

FILE: fun_inc.v

module top;
   foo #(.p(5)) f();
endmodule

module foo #(parameter p = 3);
   integer i;

   initial i = fun(1'b0);

   `include "fun.v"
endmodule

FILE: fun.v

   function fun;
      input in;
      $display("In fun, p = %0d", p);
   endfunction

Regards - Cliff

> >>module foo;
> >>   function fun;
> >>      input in;
> >>      parameter p = 3;
> >>      $display("In fun, p = ", p);
> >>   endfunction // fun
> >>   integer      i;
> >>   initial i = fun(1'b0);
> >>endmodule // foo
> >
> >Easily modified to avoid the defparam as follows:
> >
> >module top;
> >   foo #(.p(5)) f();
> >endmodule
> >
> >module foo #(parameter p = 3);
> >   integer i;
> >
> >   initial i = fun(1'b0);
> >
> >   function fun;
> >      input in;
> >      $display("In fun, p = %0d", p);
> >   endfunction
> >endmodule

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog,
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