RE: [sv-bc] @* vs. always_comb

> Maybe the reg in the module is treated as a wire, which was 
> largely the intent of SV's allowing variables to be treated 
> as wires. If so, can port collapsing occur? Port collapsing 
> is not mentioned at all in 1800. What about if I really use 
> the reg like a wire, e.g,. not in an always_comb block, but 
> rather in a continuous assignment? Is port collapsing allowed? 
> If not (since the LRM does not say it is allowed), that could 
> be an inefficiency relative to a port collapsed wire.

Actually, I can find no reference to 'port collapsing' in 1364
either. 1364 does discuss collapsing nets of different net types 
at a port connection in section 12.3.10. I assume this is what 
you are referring to. 

As far as I know, P1800 does not change the collapsing of nets
at port connections, but it did not extend this to variables.
For a net to be collapsed at a port connection, both sides of
the port connection must be nets. If one side of the port connection
is a variable, then there is no collapsing.

> Another question I have goes back to the original example, 
> "always @* sig = cond1 ? in1 : 1'bz ;".
>
> The LRM says that software tools can (probably should be "may") 
> check whether the process really represents combinational logic. 
> The question is, does such code represent combinational logic or 
> not? It is clearly not a flip-flop or a latch, but is it 
> combinational?

I would think this is combinational.