RE: [sv-bc] @* vs. always_comb

>From: "Mark Hartoog" <Mark.Hartoog@synopsys.com>

>Actually, I can find no reference to 'port collapsing' in 1364
>either. 1364 does discuss collapsing nets of different net types 
>at a port connection in section 12.3.10. I assume this is what 
>you are referring to.

Yes.  The closest the LRM gets to this term is "collapsed net",
in the following description:

"It is permissible to merge the dominating and dominated nets
into a single net, whose type shall be that of the dominating net.
The resulting net is called the simulated net, and the dominated
net is called a collapsed net."

This merging operation doesn't have a concise name in the LRM.
It is commonly called "port collapsing" in the circles where I
have discussed it.  This term probably came from Verilog-XL days.


>As far as I know, P1800 does not change the collapsing of nets
>at port connections, but it did not extend this to variables.
>For a net to be collapsed at a port connection, both sides of
>the port connection must be nets. If one side of the port connection
>is a variable, then there is no collapsing.

I would agree with this interpretation.

I think you can effectively get port collapsing for ports with
variables on both sides, by declaring the port as a ref port (just
as you can effectively force port collapsing for ports with nets
on both sides by declaring the port as an inout port).  In this
case, both variables would be the same variable, which could still
have only one continuous assignment or always_comb writing to it.

>> Another question I have goes back to the original example, 
>> "always @* sig = cond1 ? in1 : 1'bz ;".
>>
>> The LRM says that software tools can (probably should be "may") 
>> check whether the process really represents combinational logic. 
>> The question is, does such code represent combinational logic or 
>> not? It is clearly not a flip-flop or a latch, but is it 
>> combinational?
>
>I would think this is combinational.

I think that the term is being used here to mean that there are no
memory elements, and the output value is a function only of the
current combination of inputs, so I would agree.  Definitions may
also say that combinational logic can be built out of primitive
logic gates, but that is because they are defining it in a domain
that doesn't include three-state values.

Personally, I think that sort of check should be left to synthesis
tools, which can define this as combinational logic as long as they
can synthesize it as such.

Steven Sharp
sharp@cadence.com