Hi, >>As far as I know, P1800 does not change the collapsing of nets >>at port connections, but it did not extend this to variables. >>For a net to be collapsed at a port connection, both sides of >>the port connection must be nets. If one side of the port >connection >>is a variable, then there is no collapsing. > >I would agree with this interpretation. [Shalom: ] If so, does this decrease the efficiency of the simulation? >>> Another question I have goes back to the original example, >>> "always @* sig = cond1 ? in1 : 1'bz ;". >>> >>I would think this is combinational. > >I think that the term is being used here to mean that there are >no >memory elements, and the output value is a function only of the >current combination of inputs, so I would agree. Definitions >may >also say that combinational logic can be built out of primitive >logic gates, but that is because they are defining it in a >domain >that doesn't include three-state values. > >Personally, I think that sort of check should be left to >synthesis >tools, which can define this as combinational logic as long as >they >can synthesize it as such. [Shalom: ] I think it should be well enough defined, so that different tools do not interpret it differently. Thanks, ShalomReceived on Sat Dec 10 22:48:39 2005
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