RE: [sv-bc] @* vs. always_comb

Cliff,

>(2) ?: only works with single-statement assignments unless one
>is prepared
>to use lots of concatenation. Since I frequently group together
>multiple
>similar register assignments in the same always_ff block, the
>?: fails
>synthesis unless I am prepared to break up the assignments into
>multiple
>separate always_ff blocks.

[Shalom: ] Cliff, do you mean that the following does not synthesize
correctly?

always_ff @(posedge clk or posedge reset)
begin
	q1 <= reset ? '0 : d1 ;
	q2 <= reset ? '0 : d2 ;
end

Another disadvantage of the ?: style is that it is unfriendly to both
write and read when the control conditions are complex.

That said, it also has advantages, as stated.


>Suggested SV enhancement?? Add "ifx" and "elsex" keywords that
>basically do
>$isunknown (^reduction) on the tested expression and if the
>resultant
>expression is X, make X-assignments to all variables enclosed
>within the
>ifx or elsex block. A similar capability would be useful on a
>case
>statement - BTW I don't care what the keywords are ultimately
>called. These
>would basically be if-else test with built-in assertions.

[Shalom: ] This was brought up during BTF 400/401 = Mantis 1189/1190,
especially 1190. However, you add some good suggestions. I suggest you
file a Mantis on this, and reference 1189/1190.


>BTW - I know I have an interesting assertion problem in this
>example. It is
>hard to catch X's on the clk if the clk is the sample signal
>for the
>property. Perhaps Arturo has a suggested improvement.

[Shalom: ] Note that in Verilog, @(posedge clock) includes a transition
from 0 to z/x, though not from 1 to x/z.

Shalom