Re: [sv-bc] Named blocks conflicts with existing identifiers

In Verilog, an enable of a task with no arguments is required to omit
the empty ().  In SystemVerilog, it needn't omit the ().

More importantly, in SystemVerilog, even an enable of a task with
arguments, if all arguments have defaults specified, is allowed to omit
the argument list.

-- Brad

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Tuesday, December 13, 2005 2:18 AM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: [sv-bc] Named blocks conflicts with existing identifiers

So this is true for functions, but not for tasks.

Shalom

>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
>Behalf Of Brad Pierce
>Sent: Tuesday, December 13, 2005 12:27 AM
>To: sv-bc@eda.org
>Subject: Re: [sv-bc] Named blocks conflicts with existing
>identifiers
>
>
>For more about omitting method call argument lists, see --
>
>     http://eda.org/svdb/bug_view_page.php?bug_id=93
>
>"Actually, you do.  Task/function calls are known to be so
>directly due
>to parentheses.  This was in fact an issue in the initial P1800
>work where unparenthesized calls were permitted even for
>functions
>with simple names.  Due to the issues I am raising here, it was
>recognized that this would intefere with implicit net creation
>and
>the P1800 rules (see 12.4.5) were changed so that a compiler
>could
>make correct assumptions."
>
>-- Brad
>