Re: [sv-bc] @* vs. always_comb

>From: "Brad Pierce" <Brad.Pierce@synopsys.com>

>"Suppose we limit the discussion to code which is accepted by synthesis
>tools."
>
>But that subset grows with time, in response to customer demand and
>prevailing use models.  

But it is still subject to theoretical restrictions.  If it is
combinational logic, then extra evaluations with the same input
values cannot produce different results.  So it is OK if simulation
uses sensitivity that is a superset of the actual inputs used.

And of course synthesis cannot produce logic with inputs that were
not referenced in the Verilog code for the logic.  That would not be
valid synthesis.

So regardless of the growth of the synthesis subset, we can define
rules that are guaranteed to work.  Furthermore, we have some
flexibility in the exact choice of rules, since it is OK as long
as we are conservative enough.  We can use that flexibility to try
to optimize for things like simulation performance.  If we aren't
sure what is best, or are concerned that it may be different in
different implementations, or change over time, we can pass that
flexibility on to the implementers.

Steven Sharp
sharp@cadence.com