As I understood it, the only reason that packed arrays of integer were not allowed was fear of backward incompatibility with legacy code that used declarations like integer [7:0] i; This was illegal, but Verilog-XL accepted it and ignored the range. If this were allowed in SystemVerilog, but with a different meaning, it would change the meaning of this legacy (illegal) code. Since a typedef for integer could never appear in legacy code, I don't see how this problem applies in that case. And since the predefined integer types are all packed types, I don't see any other technical reasons why it should not be legal to use them as elements in packed arrays. Steven Sharp sharp@cadence.comReceived on Fri Dec 16 10:57:39 2005
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