According to 12.4.3, "To handle common cases or allow for unused arguments, SystemVerilog allows a subroutine declaration to specify a default value for each singular argument." So, the following is not legal? typedef int T [255]; function automatic foo ( T in1, in2 = '{default:0} ) ; foreach (foo[i]) foo[i] = in1[i] + in2[i]; endfunction : foo -- BradReceived on Sun Dec 18 18:01:51 2005
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