RE: [sv-bc] why is it ILLEGAL ?

Nasim,

I'll take a crack at this. I believe the answer has to do with heritage,
parsing and with parameterization.

Many of the procedural aspects of Verilog come straight from the Pascal
language (declaration order rules, begin/end, case statement), and many
of the syntax rules are based on parsing Pascal (Although this rule is
common in many other languages).

The problem for the parser is that it will recognize the identifier as
being part of a new declaration before it has fully understood what the
type is. For example:

reg x;
reg unsigned x;

These are the same matching types, but type matching usually comes much
later in the compilation process. The compiler would want to store only
one symbol table entry for 'x'.

Then there is parameterization:

parameter B= 5;
reg [0:5] x;
reg [0:B] x;

Are these declarations the same type? Sometimes.

Hope this helps,

Dave




> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Nasim
> Hussain
> Sent: Sunday, December 18, 2005 11:44 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] why is it ILLEGAL ?
> 
> hi-
> 
> i had a small question, it is more related to verilog data types, but
> thought i would ask it here anyway, since i have a feeling it will
also
> apply to SV data types.
> 
> 
> this is with regards to the following line
> 	(taken from IEEE Std. 1364-2001)
> 
> 
> section 3.2.1 and 3.2.2 under chapter 3 ("data types") both say:
> 
> 	"it is illegal to redeclare a name already declared by a net,
> parameter, or variable declaration"
> 
> 
> i am failing to understand why it is ILLEGAL ? for example, i don't
see
> anything wrong with the following:
> 
> 
> 	module top();
> 	wire x;
> 	...
> 	wire x;
> 		cpu U1 (.a(x) ...)
> 		mcu U2 (.b(x) ...)
> 	endmodule
> 
> 
> yes, wire x is declared twice, but it is of the SAME data type. i
don't
> think this should even be a warning, forget an error! anyhow, one
> simulator says it is a warning during compilation (OK, i accepted
that,
> but with reservations), whereas another one (well 2 of them actually)
> straight said "no sir, that is an error!", and quits.
> 
> it isn't like i have "wire x;" and then "reg x;"... which, despite
it's
> being redeclared, IMO should be inferred from the logic it is being
used
> to construct. for example-
> 
> 	wire x;
> 	reg x;
> 	always @(posedge clk)
> 		q <= d;
> 
> it is obvious here that the user intends to create a
+ve-edge-triggered
> FF... meaning the compiler SHOULD accept it rightfully as a reg (i am
> not saying "assign x = ", in which case yes, the compiler should flag
it
> as an error!).
> 
> then again, under section 12.6 (scope rules), i see in the very 1st
> paragraph - "an identifier shall be used to declare only one item
within
> a scope. this rule means it is ILLEGAL to declare two or more
variables
> that have the SAME name... "
> 
> come on... are they being serious here ? :D
> 
> will someone kindly tell me what is wrong with the following:
> 
> 	module top();
> 	reg a;
> 	reg a;
> 	reg a;
> 	reg a;
> 	reg a;
> 	endmodule
> 
> -nasim
> 
> --
> ----------------------------------------------------------------------
> Nasim Hussain           | Life is short,   ---     _ o     _~o     _ o
> UltraSPARC Verification |   go wherever  ----    _`\<,   _`\<,   _`\<,
> SUN Microsystems, Inc.  |     you want...  ---  ( )/( ) ( )/( ) ( )/(
)
> work - (408) 720-4927   |        do whatever
> home - (650) 967-7730   |           you want...