RE: [sv-bc] Differences between 1800 and 3.1a

Yes.

I can give a summary of the changes in 1364.

 

Shalom

 

________________________________

From: Michael Smith [mailto:michael.smith@doulos.com] 
Sent: Tuesday, December 20, 2005 12:01 PM
To: Bresticker, Shalom; sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
Subject: RE: [sv-bc] Differences between 1800 and 3.1a

 

Who is in charge? Johni (SV)? and Tom (Verilog)?

	-----Original Message-----
	From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
	Sent: 20 December 2005 09:16
	To: Michael Smith; sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
	Subject: RE: [sv-bc] Differences between 1800 and 3.1a

	Going through the documents is not very practical.

	 

	For SV, there is such a version.

	 

	For 1364, such a version was produced for a non-final draft of
1364-2005.

	 

	For good order, you should get official approval to receive
these. Personally, I would think that if you purchase or have access to
the final version, you should be allowed access to the change documents
as well, but I'm not in charge.

	 

	Shalom

	 

	 

	
________________________________


	From: Michael Smith [mailto:michael.smith@doulos.com] 
	Sent: Tuesday, December 20, 2005 11:05 AM
	To: Bresticker, Shalom; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org
	Subject: RE: [sv-bc] Differences between 1800 and 3.1a

	 

	As much as possible! Ideally versions of the IEEE LRMs with
change bars. Failing that, a comprehensive list of "significant" 

	differences from a user's point of view. (I am updating Doulos's
Systemverilog Golden Reference Guide.) Obviously I can go through the
documents myself, but if someone's already done the work, it would be a
great help.

	 

	Thanks,

	Mike

		-----Original Message-----
		From: Bresticker, Shalom
[mailto:shalom.bresticker@intel.com]
		Sent: 20 December 2005 08:54
		To: Michael Smith; sv-bc@eda.org; sv-ac@eda.org;
sv-ec@eda.org
		Subject: RE: [sv-bc] Differences between 1800 and 3.1a

		How much detail do you want?

		 

		Shalom

		 

		
________________________________


		From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]
On Behalf Of Michael Smith
		Sent: Tuesday, December 20, 2005 10:41 AM
		To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org
		Subject: [sv-bc] Differences between 1800 and 3.1a

		 

		Is there anywhere a list of the differences between
IEEE-1800 SystemVerilog and 3.1a?

		And between Verilog-2005 and Verilog-2001?

		 

		Thanks,

		Michael Smith,

		Doulos Ltd.