RE: [sv-bc] "loop/looping" terminology inconsistency

Yulik,

 

I don't think this was deliberate. In the Superlog donation, it was just
entitled "Loops". It looks like the SystemVerilog 3.0 committee changed
it to "Loop statements". I agree that it would be nice to have more
consistency and that "looping" is probably more a proper term, but I
would rather spend the effort merging the two specifications. That means
getting through the rest of errata as quickly as possible.

 

Dave

 

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Feldman, Yulik
Sent: Monday, December 26, 2005 12:48 AM
To: sv-bc@eda.org
Subject: [sv-bc] "loop/looping" terminology inconsistency

 

Hi,

 

FYI, there is an inconsistency in the terminology used in 1364 and 1800:

 

In 1364, the section 9.6 is titled "Looping statements"

In 1800, the section 10.5 is titled "Loop statements"

 

Was this deliberate terminology change or an oversight?

 

--Yulik.