RE: [sv-bc] event regions

Hi, thanks.

I have not yet studied your reply in detail, but I have a question.

Why do you say that cbAssertionSuccess and 'expect' execute in the
Post-Observed region?

I'm not arguing, just trying to understand.

9.3 says,
" The Post-observed region provides for a PLI callback control point
that allows PLI application routines to
read values after properties are evaluated (in Observed or earlier
region).
NOTE-The PLI currently does not schedule callbacks in the Post-observed
region."

And it is described as purely a PLI region.

Is it because 17.16 says,
"The statement following the expect is
scheduled to execute after processing the Observe region in which the
property completes its evaluation."?

That does seem ambiguous regarding its scheduling.

By the way, the word "Post-observed" in the paragraph preceding 9.4
seems to have a special hyphen instead of a regular one. The result is
that when you search for "post-observed" in Acrobat, it does not show,
only when you search for "postobserved" without a hyphen.

Shalom



> -----Original Message-----
> From: Nasim Hussain [mailto:Nasim.Hussain@Sun.COM]
> Sent: Friday, December 30, 2005 11:33 AM
> To: Bresticker, Shalom
> Subject: Re: [sv-bc] event regions
> 
> hi-
> 
> 
> hmmm... you are right, i am confused, too. :(
> 
> 
> what i know is that ALL of preponed, preactive, preNBA,
> postNBA,
> postobserved, and postponed can have VPI callbacks.
> 
> 
> here is my breakdown:
> 
> 	- preponed:	VPI (i.e. cbStmt) and SV (sampling with #1step)
> 	- preactive: 	VPI only (i.e. cbAtStartOfSimTime)
> 	- preNBA:	VPI only (i.e. cbNBASynch)
> 	- postNBA:	VPI only (i.e. cbReadWriteSynch)
> 	- postobserved: VPI (i.e. cbAssertionSuccess) and SV
> ('expect')
> 	- postponed:	VPI (i.e. cbReadOnlySynch) and SV ($monitor)
> 
> 
> 
> sampling (of data) is possible for 2 entities:
>  |
>  |
>  |
>  |---> (i) sampling of data for sequences/properties
> (assertions)
>  |        |
>  |        |
>  |        |
>  |        |----> clocking block w/ explicit #0 input skew.
> simulator
>  |        |      will sample inputs in "postponed" region of
> previous
>  |        |      time slot
>  |        |
>  |        |
>  |        |
>  |        |----> clocking block w/ skew of #1step (implicit
> behavior).
>  |               simulator will sample inputs in "preponed"
> region
>  |               of current time slot
>  |
>  |
>  |
>  |
>  |
>  |---> (ii) sampling of data regarding program block processes,
>           | or coverage points (functional coverage),
>           | or cover statement (assertion coverage)
>           |
>           |
>           |
>           |----> clocking block w/ explicit #0 input skew.
> simulator
>           |      will sample inputs in "observed" region of
> previous
>           |      time slot
>           |
>           |
>           |
>           |----> clocking block w/ skew of #1step (implicit
> behavior).
> 		 simulator COULD sample inputs in "postponed" region
> 		 of previous time slot or in "preponed" region of
> 		 current time slot
> 
> 
> 
> by the way, i *never* liked the name inactive, i typically
> refer to it
> in my presentations/slides as 'postactive'! :D
> 
> 
> -nasim
> 
> 
> 
> Bresticker, Shalom wrote On 12/29/05 06:43 AM,:
> > There is some unclearness in Section 9.
> >
> > First, it seems that the Preponed and Postponed regions are
> both PLI and non-PLI regions, is this correct?
> >
> > If so, Figure 9-1 confuses this by showing each region as
> either PLI or implicitly non-PLI.
> >
> > Also, #1step is described in 9.3, "Conceptually, this #1step
> sampling is identical to taking the data samples in the
> Preponed region of the current time slot."
> >
> > However, in 15.2, it says, "A 1step input skew allows input
> signals to sample their steady-state values in the time step
> immediately before the clock event (i.e., in the preceding
> Postponed region)", and in 15.12, "If the input skew is not an
> explicit #0, then the value sampled corresponds to the signal
> value at the Postponed region of the time step skew time units
> prior to the clocking event (see Figure 15-1 in 15.3)."
> >
> > This is confusing.
> >
> > Thanks,
> > Shalom
> >
> > Shalom Bresticker
> > Intel Jerusalem LAD DA
> > +972 2 589-6852
> > +972 54 721-1033
> > I don't represent Intel
> >
> >
> 
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