Re: [sv-bc] Figure 9-1 blue arrow

Shalom,

I don't think the blue arrow in Fig. 9-1 is supposed to be there.  CC'ing in the sv-ec, because it is their issue, Mantis 722.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Sunday, January 01, 2006 4:50 AM
To: sv-bc@eda.org
Subject: [sv-bc] Figure 9-1 blue arrow

In Figure 9-1, "The SystemVerilog flow of time slots and event regions", there is a blue arrow from after re-inactive to before active.

Should it be there?

If so, why is it blue and what does the arrow represent?

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033
I don't represent Intel