Re: [sv-bc] structure literal example in standard

>Verilog explicitly permitted repeat concatenation of function calls
>to evaluate by replicating the result of one function call.

And V2005 mandates it.  The updated LRM says

"    When a replication expression is evaluated, the operands shall be
"evaluated exactly once, even if the replication constant is zero. For
"example:
"
"       result = {4{func(w)}} ;
"
"would be computed as
"
"       y = func(w) ;
"       result = {y, y, y, y} ;

-- Brad