>From: "Michael (Mac) McNamara" <mcnamara@cadence.com> >However, this does result in a disservice to the synthesis implementer: there is no way for the synthesis programmer to know what order was chosen by the simulator programmer, and hence to generate gates which match the results simulated by the simulator. I don't think this is a real issue in practice. If the evaluation has side effects that create an order dependency, I don't think that it qualifies as synthesizable code. But Brad would know about that better than I would. It certainly doesn't qualify as reasonable code, and nobody should ever write code that does this. >Moreover, this becomes yet another place where two simulators could give different results for the same design & stimulus, and yet both be standard compliant. I wouldn't have had a problem if the LRM had specified that the conditions be evaluated from top to bottom in order. But I don't think it will cause significant trouble. Nobody should be writing code that has side effects from evaluating a condition. Steven Sharp sharp@cadence.comReceived on Thu Jan 12 17:03:29 2006
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