[sv-bc] A few Mantis issues

Hello All,

I created and uploaded proposals for two more easy issues:

   http://www.eda.org/svdb/bug_view_page.php?bug_id=0001260
   http://www.eda.org/svdb/bug_view_page.php?bug_id=0001261

We can review these and vote on them next meeting.

***

On issue http://www.eda.org/svdb/bug_view_page.php?bug_id=0001255,
next meeting I would like to move that we close the issue as 
already addressed in Clause 11.6.6 of 1364-2005_D7:

   "Primitive terminals are different from module ports. Primitive
output and inout terminals shall be connected
directly to 1-bit nets or 1-bit structural net expressions (see
12.3.9.2), with no intervening process that could
alter the strength. Changes from primitive evaluations are scheduled as
active update events on the
connected nets. Input terminals connected to 1-bit nets or 1-bit
structural net expressions are also connected
directly, with no intervening process that could affect the strength.
Input terminals connected to other kinds
of expressions are represented as implicit continuous assignments from
the expression to an implicit net that
is connected to the input terminal."

This is newly added text, which appears to adequately address
Shalom's concerns in Mantis #1255.  Additionally, I text-searched
the PDF LRM for "terminal", and found all uses were consistent with:

 - primitive terminals
 - specify block terminals
 - terminals given to timing check system tasks

***

Matt, can you please add these three items to next meeting's agenda,
along with the other items with proposal from my earlier mail that
stemmed from our last meeting?

Thanks and Regards,
Doug