RE: [sv-bc] logical operation on vectors

Nasim,

In your case x and y are packed vectors, therefore when applying a
logical operator between them a reduction or will be done on each
operand.
Your RTL will be equivalent to
	always_comb begin
	   a = (|x) || (|y);
	   b = (|x) && (|y);
	end


Dan Jacobi
Intel Corpoartion
Tel : (503) 712-3207

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Nasim Hussain
Sent: Wednesday, January 25, 2006 10:30 AM
To: sv-bc@eda.org
Subject: [sv-bc] logical operation on vectors


hello-

i had a small question. it also applies to verilog 1995 (and 2001), but
i am not sure i fully understand how it works.


let us assume i have something like the following.
(note: instead of | and &, i "mistakenly" used || and &&)


	logic [1:0] x,y;
	logic a,b;

	always_comb begin
	   a = x || y;
	   b = x && y;
	end


will simulator's parser issue a warning or an error as i am doing a
logical (and not bit-wise) OR / AND operation on 2 vectors ?


if the compiler issues a warning and continues, then what would the
simulator output be at runtime when x=2'b10 and y=2'b10 ?

i see it says a=1 and b=1. how does it work ? does it get treated like:


	always_comb begin
	   a = !(x == 2'b00) || !(y == 2'b00);
	   b = !(x == 2'b00) && !(y == 2'b00);
	end


i always used to think maybe it would do a bit-wise OR / AND but for the
LSBs only... and so, i was expecting a=0 and b=0 for the above stimulus.

but it appears i am wrong.

thanks,